1. Field of the Invention
This invention relates to thyristors in general and, more particularly, to lateral thyristors having MOS gates for use in integrated circuits or the like.
2. Description of the Prior Art
In the field of integrated power electronics, it is desirable to have on a single integrated circuit at least one power handling device and the necessary control circuitry to drive the device. In particular, it is especially desirable that the power handling device be controllable by a voltage instead of by a current. The advantage of voltage control circuitry is the increase in the power handling capacity thereof, compared to current control circuits. For example, an exemplary conventional power handling device, a thyristor, is usually a current controlled device. The current necessary to switch the thyristor on or off may well exceed the current driving capacity of complementary metal-oxide-semiconductor (CMOS) logic circuits. However, if the thyristor is designed to be switched with a voltage, conventional CMOS logic can directly drive even very high power thyristors. A voltage controlled thyristor is commonly known as a MOS controlled thyristor or MCT.
An exemplary MOS controlled thyristor, which is readily intergratable into an IC, is disclosed in "Insulated-Gate Planar Thyristors: I-Structure and Basic Operation," by J. D. Plummer and B. W. Scharf, IEEE Transactions On Electron Devices, Vol. ED-27, No. 2, February 1980, pp 380-387. In FIG. 11 of Plummer's article, a lateral MOS controlled thyristor MCT is shown having separate gates for the turning "on" and turning "off" the thyristor. For clarity, Plummer's thyristor has been simplified and redrawn, as presented in FIG. 3. Thus, MCT 30 has an n-type epitaxial layer (40) with first and second p-type regions (31, 32) formed in the major surface of the epitaxial layer 40. A third n-type region 33 is formed within the first region 31 as the cathode of the thyristor. Similarly, another n-type region 35 is formed in the second region 32. Regions 32 and 35 are electrically connected together as the anode of the MCT 30. Another p-type region 36 is added and electrically connected to the third region 33 as part of the cathode. A first conductive layer 37 is disposed over, and is insulated from, portions of the regions 31, 33, and the epitaxial layer 40 to form an n-channel DMOS transistor for the "on" gate of the MCT 30. A second conductive layer 39 is disposed over, and is insulated from, the first region 31 and the epitaxial layer 40 between the regions 33 and 36 to form a PMOS transistor for the "off" gate of the MCT 30.
The Plummer MCT suffers from a parasitic PNP transistor formed by p-type region 36, n-type epitaxial layer 40, and p-type region 32. Since the on-gate (first conductive layer 37) cannot turn off the thyristor 30, the parasitic PNP is unavoidable with this structure since the region 36 and the off-gate (second conductive layer 39) must be provided.
The parasitic PNP gives rise to two dominant defects which limit the performance of the MCT 30: limited maximum current that the MCT can conduct while still allowing the off gate (39) to turn off the MCT (referred to as the maximum turn-off current), and increased forward voltage drop of the MCT 30.
The lowered maximum turn-off current defect results from a "sneak" path for current through the parasitic PNP transistor. The reduced maximum turn-off current is further decreased by the relatively high channel resistance of the PMOS transistor, limiting the amount of current that can be shunted to turn off the thyristor.
The increased forward voltage drop across the MCT results from the parasitic PNP transistor drawing off a large fraction of the injected anode hole current, reducing the gain of the thyristor. The reduced gain does not allow the thyristor to conduct as "hard" as would otherwise be possible. The reduced gain causes the forward voltage drop to be significantly greater than what could be obtained with a conventional thyristor.
An exemplary MOS controlled thyristor which does not suffer from the above defects as a result of a parasitic PNP transistor is disclosed in "MCTs-Thyristors For the Future," by Dr. V. A. K. Temple, Powertechnics Magazine, November 1989, pp. 21-24. In particular, FIG. 4 of Temple's article shows the structure of this MCT. However, this structure is substantially vertically oriented, making it unsuitable for integration with other circuits into an integrated circuit (IC).